用FPGA制做呼吸灯效果的LED「建议收藏」

所谓呼吸效果就是指灯从灭缓慢的变亮，然后从亮缓慢的变暗，就像人的呼吸一样，如此循环。这时有人会说，这个容易，调节LED两端电压就行了，由于FPGA是数字电路，输出的是数字信号，非‘’0‘’即‘’1‘’，所以不能用改变输出引脚电压的方法来达到目的。

我们可以控制高低电平输出的时间，可以使LED灯在单位时间内亮的时间依次增加，形成逐渐变亮的效果.也就是常说的PWM(脉宽调制).

PWM原理

新建工程，在生成的代码模板中做如下修改：

library IEEE, UNISIM;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

use IEEE.MATH_REAL.all;

use IEEE.std_logic_1164.all;

use IEEE.numeric_std.all;

use UNISIM.vcomponents.all;

— Uncomment the following library declaration if using

— arithmetic functions with Signed or Unsigned values

–use IEEE.NUMERIC_STD.ALL;

— Uncomment the following library declaration if instantiating

— any Xilinx primitives in this code.

–library UNISIM;

–use UNISIM.VComponents.all;

entity pwm is

Port ( clk_i : in STD_LOGIC;

pwm_o : out STD_LOGIC);

end pwm;

architecture Behavioral of pwm is

signal cnt_r : std_logic_vector(22 downto 0) := (others=>’0′);

signal clk_1: std_logic;

signal Reversal: std_logic :=’0′;

signal duty_s : std_logic_vector(7 downto 0):= (others=>’0′);

signal timer_r : std_logic_vector(7 downto 0):= (others=>’0′);

begin

process(clk_i) is

begin

if rising_edge(clk_i) then

cnt_r <= cnt_r + 1;

end if;

end process;

clk_1 <= cnt_r(15);

process(clk_1) is

begin

if clk_1’event and clk_1 = ‘1’ then

if Reversal = ‘0’ then

if duty_s = “11111111” then

Reversal <= ‘1’;

else

duty_s <= duty_s + 1;

end if;

else

if duty_s = “00000000” then

Reversal <= ‘0’;

else

duty_s <= duty_s – 1;

end if;

end if;

end if;

end process;

process(clk_i)

begin

if rising_edge(clk_i) then

pwm_o <= ‘0’;

timer_r <= timer_r + 1;

if timer_r < duty_s then

pwm_o <= ‘1’;

end if;

end if;

end process;

end Behavioral;

综合得到位流文件，然后配置FPGA即可看到如下效果